Patent attributes
The present invention provides a refresh controller for embedded DRAM, configured to receive an external access signal and generate refresh enabling signal REFN, refresh address signal CRA and confliction signal, said embedded DRAM comprising a plurality of memory groups, said controller comprising: a status controlling module that generates refresh enabling signal REFN and last refresh signal last_ccr according to the refresh interval and clock cycles; a refresh searching module that searches in said plurality of memory bank groups for at least one memory bank group that is to be refreshed in the refresh interval, and generates refresh address signal CRA according to the external access signal and the searched memory bank group; a scoreboard module that records the status of each of said plurality of memory bank groups according to said refresh address signal CRA and external access signal; and a confliction detecting module that generates confliction signal according to said external access signal, last refresh signal last_ccr and the status of each of said memory banks. A corresponding refresh controlling method is also provided in the present invention.
