Patent attributes
In order to provide a semiconductor memory apparatus which can adjust the locked loop circuit such as a DLL in detail after producing the semiconductor memory apparatus, and moreover, which can adjust the locked loop circuit by using a measuring apparatus which has a low testing frequency, an exclusive-OR circuit generates an adjusting clock signal TCLK obtained by multiplying a frequency of a pair of test clock signals which respectively have a phase difference. A DLL circuit inputs the adjusting clock signal TCLK in place to an external clock signal CLK. The counter circuit counts the control clock signal CCLK outputted from the DLL circuit for a predetermined time. A comparator compares a counted value to an expected value and outputs a comparison result. A phase adjusting circuit outputs an adjusting signal to a delay circuit inside the DLL circuit based on the comparison result outputted from the comparator, and adjusts a phase of the control clock signal CCLK outputted from the DLL circuit.
