Patent attributes
A memory controller includes a first calculation circuit configured to calculate an intermediate calculated value of an error correction code by using the head byte to a specified byte of a data in a process of calculating the error correction code for the data read from a memory, a data storage circuit configured to store the intermediate calculated value, a changing circuit configured to change data in a following part of the specified byte of the data, a second calculation circuit configured to calculate another error correction code by using the intermediate calculated value and the data in the following part including the changed data, and a data transferring circuit configured to transfer the changed data and the error correction code calculated in the second calculation circuit to the memory.
