US Patent 7889561 Read operation for NAND memory

Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to a source line selectively coupled to a bit line through a string of series-coupled non-volatile memory cells containing a memory cell targeted for reading, and where a second, different, potential is supplied to other source lines selectively coupled to the bit line through other strings of series-coupled non-volatile memory cells not containing the target memory cell. Supplying a different potential to the other source lines facilitates mitigation of current leakage between the other source lines and the bit line while sensing a data value of the target memory cell.