Patent attributes
Latch-up of CMOS devices (20, 20′) is improved by using a structure (40, 40′, 80) having electrically coupled but floating doped regions (64, 64′; 65, 65′) between the N-channel (44) and P-channel (45) devices. The doped regions (64, 64′; 65, 65′) desirably lie substantially parallel to the source-drain regions (422, 423; 432, 433) of the devices (44, 45) between the Pwell (42) and Nwell (43) regions in which the source-drain regions (422, 423; 432, 433) are located. A first (“N BAR”) doped region (64, 64′) forms a PN junction (512) with the Pwell (42), spaced apart from a source/drain region (423) in the Pwell (42), and a second (“P BAR”) doped region (55, 55′) forms a PN junction (513) with the Nwell (43), spaced apart from a source/drain region (433) in the Nwell (43). A further NP junction (511) lies between the N BAR (64) and P BAR (65) regions. The N BAR (64) and P BAR (65) regions are ohmically coupled, preferably by a low resistance metal conductor (62), and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).
