US Patent 7893530 Circuit substrate and the semiconductor package having the same

The present invention relates to a circuit substrate comprising an upper surface, a first layout area, a second layout area, and a third layout area. The first layout area is on the upper surface, and has a plurality of first electrical contacts. The second layout area is on the upper surface, and has a plurality of second electrical contacts. The third layout area is on the upper surface, and has a plurality of third electrical contacts. The second and the third electrical contacts that have the same electrical property are electrically connected to each other. Thus, the circuit substrate can be applied to memory chips with different size.