Patent attributes
A data signal generating apparatus with a data output unit for outputting m-bit parallel data and a data synchronization clock signal synchronized with the parallel data in response to a data request signal produced by dividing the frequency of a reference clock signal by “m.” An m:1 multiplexer for receiving the parallel data in response to a latch signal produced by dividing the frequency of the reference clock signal by “m,” and outputting, at a rate of the reference clock signal, data synchronization serial data. Synchronization means for comparing the phases of the data synchronization clock signal and the latch signal, for synchronizing the parallel data with the latch signal, and for producing a control signal, and which delays, on the basis of the control signal, the reference clock signal or a divided clock signal (dividing the frequency of the reference clock signal by “m” or less).
