Patent attributes
A switched current memory cell includes a current source 100 having one end connected to an operation power source (Vdd) stage, a current memory circuit unit 200 that stores an input current; which is inputted in a sampling mode of the current from the current source 100, during a hold mode, maintains the current value stored in the hold mode, and outputs the stored current in an output mode, an input switch SW10 that is turned on in the sampling mode to transfer an input current to the current memory circuit unit 200, and turned off in the hold mode, an output switch SW20 that is turned on in the output mode to output current from the current memory circuit unit 200, and a current cut circuit unit 300 that connects a current path between the operation power source Vdd stage and the current source 100 in the input mode and output mode, and separates the current path between the operation power source Vdd stage and the current source 100 in the hold mode.
