US Patent 7898087 Integrated chip carrier with compliant interconnects

An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top surface connected to the bottom surface of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a plurality of through vias from the bottom surface of the carrier to the top surface of the carrier layer. Each through via includes a collar exposed at the top surface of the carrier, a pad exposed at the bottom surface of the carrier, and a post disposed between the collar and the pad. The post extends thorough a volume of space.