Patent attributes
Some embodiments provide a method of digital logic design and digital logic testing of logic under test, the logic including latches, the latches including measure latches, which are latches that measure focal faults more than other latches, and care bit latches, which are latches that require specific input values to test a fault, wherein a focal fault is a randomly selected untested fault in the logic under test, the method comprising generating test patterns for the logic under test; fault simulating the test patterns on the logic under test; ranking measure latches based on the number of focal faults they respectively measure; and tracing back a number of levels from at least some of the highest ranked measure latches and inserting test observe latches. Other methods and systems are also provided.
