Patent attributes
Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) arc disclosed. One embodiment of the present invention includes repairable IO circuitry along a right, left, or inner column of an IC. Another embodiment includes repairable IO circuitry along a top, bottom, or inner row of an IC. In one embodiment, normal and redundant mode routing is provided between IO buffer circuits and IO register circuits. In another embodiment, normal and redundant mode routing is also provided between IO register circuits and routing to core regions of the IC. One embodiment provides normal and redundant mode routing between two or more IO registers that may span more than one row and/or more than one IO block. One embodiment provides normal and redundant mode routing for different types of IO registers. In some embodiments, redundant mode IO connections shift along with redundant mode connections in a core logic region of the IC. In other embodiments, redundant mode IO connections operate to repair IO circuitry independently of any redundancy scheme in the IC's core regions.
