Patent attributes
Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.
