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US Patent 7904265 Circuits and methods for calibrating a delay element

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Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
7904265
Date of Patent
March 8, 2011
Patent Application Number
12052403
Date Filed
March 20, 2008
Patent Citations Received
‌
US Patent 11940836 Dual chip clock synchronization
0
Patent Primary Examiner
‌
Andrew Schechter
Patent abstract

A controllable delay element is coupled in parallel with a calibration circuit. The calibration circuit receives a periodic reference signal and generates a series of sample voltages responsive to a time-varying analog voltage, the periodic reference signal, and the delayed periodic signal at the output of the controllable delay element. The calibration circuit distributes the series of sampled voltages for determining the components of a first vector. The first vector components are used to calculate the phase that results from a control signal applied to the controllable delay element. After the control signal is modified, a second vector is used to calculate the phase that results from the control signal. The delay can be determined by the product of the period of the reference signal and the difference in phase.

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