Patent attributes
The disclosure of this application enhances the data writing speed of an electrically erasable and writable semiconductor memory. In a semiconductor storage device of this application, at a time of writing data, when a positive voltage lower than a voltage at control gate 30 is applied to potential control gate 28 formed inside tunnel oxide film 360 between p channel 22 of a transistor and floating gate 32, a potential barrier between p channel 22 of the transistor and floating gate 32 is lowered, and a time required for storing an electron in floating gate 30 is reduced. After data is stored, when 0 V or a negative voltage is applied to the potential control gate, a potential barrier for an electron moving from the floating gate to the channel of the transistor increases, thereby preventing erasure of data.
