US Patent 7912997 Direct memory access engine

A direct memory access engine is described. The direct memory access engine has a transmit channel coupled to a transmit interface, a receive channel coupled to a receive interface, an arbiter coupled to both the transmit channel and the receive channel, and a set of queues coupled to the arbiter. The set of queues has command buffers, transmit buffers, and receive buffers. A direct memory access-to-processor bus interface is coupled to the set of queues. The transmit buffers are for first separate read and write requests. The receive buffers are for second separate read and write requests which are independent of the first separate read and write requests.