Patent attributes
The present invention relates to a data processing system is provided which comprises at least one first processing unit (CPU), at least one second processing unit (PU), at least one memory module (MEM), and an interconnect. The memory module (MEM) serves to store data from said at least one first and second processing unit (CPU, PU). The interconnecting means couples the memory module (MEM) to the first and second processing units (CPU, PU). In addition, an arbitration unit (AU) is provided for performing the arbitration to the memory module (MEM) of the first and second processing units (CPU, PU). The arbitration is performed on a time window basis. A first access time during which the second processing unit (PU) has accessed the memory module and a second access time which is still required by the second processing unit (PU) to complete its processing are monitored during a predefined time window by the arbitration unit (AU). The second access time is compared to the remaining access time in the time window and if the remaining access time is larger than the second access time, the arbitration unit (AU) allows said at least one first processing unit (CPU) to access the memory module in said time window. Otherwise, the arbitration unit (AU) restricts the access of the at least one first processing units (CPU) and allows the at least one second processing unit (PU) to access the memory module (MEM).
