Patent attributes
Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide background thread processing in a multithread digital signal processor for backgrounding and other background operations. The method and system form a background thread interrupt as one of a plurality of interrupt types, the background thread interrupt initiates a low-priority background process using one of a plurality of processing threads of a multithread digital signal processor. The process includes storing the background thread interrupt in an interrupt register and a background processing mask for associating with a processing thread of the multithread digital signal processor, which associates with at least a subset of said plurality of processing threads. Upon sensing a cache miss in one of the processing threads during multithread processing, the interrupt register issues the background thread interrupt and the digital signal processor initiates background processing using one of the processing threads having an associated background processing mask.
