Patent attributes
Integrated circuits are provided that have memory arrays. The memory arrays may include rows and columns of data byte storage locations. To implement algorithms that that process data subwords, a memory array may be partitioned into individual memory banks each of which has its own associated data register and its own associated address decoder. Each address decoder may receive address signals from an associated multiplexer. Address mapping circuits may be used to distribute address signals to multiplexer inputs using an non-blocking memory architecture. The memory architecture allows collections of data bytes to be written and read from the memory array using column-wise and row-wise read and write operations. The data bytes that are written to the array and that are read from the array may be stored in adjacent data byte locations in the array.
