Patent attributes
Embodiments of the methods and systems of the present invention may provide improved methods for the verification of an integrated circuit where a verification project for an integrated circuit may be created by selecting a set of intent units corresponding to the integrated circuit design from a library of intent units and linking these intent units to the integrated circuit design. Specifically, in one embodiment each of these intent units may comprise a corresponding code component and text component such that from the set of intent units selected and configured based on the integrated circuit design a verification plan can be generated from the text components of the corresponding intent units while a testbench can be generated from the code components of the corresponding intent units. This testbench can then be used to generate a model for testing the integrated circuit design.
