US Patent 7920397 Memory device having bit line leakage compensation
Patent 7920397 was granted and assigned to NetLogic Microsystems on April, 2011 by the United States Patent and Trademark Office.
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A memory device operates in a calibration mode during which the effects of bit line leakage current are measured and to operate in a normal mode during which the bit line current is adjusted to compensate for leakage according to the results of the calibration mode. In the calibration mode, a leakage-free sense operation is performed to determine the differential voltage generated on the bit lines in response to a data value. Then, a leakage-susceptible test read operation is performed to determine the differential voltage generated on the bit lines in response to the data value. A detection circuit measures the difference between the differential voltages generated in the leakage-free and leakage-susceptible test read operations to generate a compensation signal, which subsequently adjusts the bit line compensation current during the normal mode.
US Patent 07920397 Memory device having bit line leakage compensation US Patent 7920397 Memory device having bit line leakage compensation
US Patent 07920397 Memory device having bit line leakage compensation
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