Patent attributes
A pair of measuring switches S21, S22 is interposed between both terminals of a capacitor C, and inputs T1, T2 of A/D converters 11c, 11d via resistors R1, R2. A pair of measuring switches S23, S24 is interposed between both inputs T1, T2 and a ground. The CPU 12a controls the measuring switches S21 to S24 so that when a terminal “a” of the capacitor C is positive charged, while the other terminal “b” of the capacitor C is grounded, both terminals “a” and “b” are respectively connected to the inputs T1 and T2. The CPU 12a controls the measuring switches S21 to S24 so that when the terminal “b” of the capacitor C is positive charged, while the terminal “a” of the capacitor C is grounded, both terminals “a” and “b” are respectively connected to the inputs T1 and T2.
