Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
William J. Hurley0
Orazio P. Forlenza0
Phong T. Tran0
Thomas J. Knips0
Donato O. Forlenza0
Gary William Maier0
Joseph Eckelman0
Date of Patent
April 19, 2011
0Patent Application Number
120355150
Date Filed
February 22, 2008
0Patent Primary Examiner
Patent abstract
A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.
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