US Patent 7932542 Method of fabricating an integrated circuit with stress enhancement

A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.