Patent attributes
In a semiconductor integrated circuit including a plurality of cells, a supplementary power-supply wire is disposed between a lattice-shaped upper power-supply wire and a lower cell power-supply wire for cases in which power is supplied from the upper power-supply wire to the lower cell power-supply wire. The supplementary power-supply wire and the lower cell power-supply wire are connected by two vias. The supplementary power-supply wire and the upper power-supply wire are connected by a single via. Current from the supplementary power-supply wire is divided by the two vias and then supplied to the lower cell power-supply wire. Therefore, when power is supplied from the upper power-supply wire to the lower cell power-supply wire, current concentration at the connection points of the lower cell power-supply wire to the vias is decreased, thereby reducing wire breaks caused by EM (electro migration).
