US Patent 7936757 Packet fragment reassembly

An apparatus for packet fragment reassembly includes a memory and a fragment processing block coupled to the memory. The memory caches information contained in the headers of a plurality of packet fragments, wherein the plurality of packet fragments are identified as belonging to a particular packet. The fragment processing block directly performs operations to each packet fragment according to the information cached in the memory and a predetermined standard, wherein the information cached in the memory is used to track whether all packet fragments associated with the particular packet have been received at the apparatus.