US Patent 7937647 Error-detecting and correcting FPGA architecture
Patent 7937647 was granted and assigned to Actel (company) on May, 2011 by the United States Patent and Trademark Office.
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A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.
US Patent 07937647 Error-detecting and correcting FPGA architecture US Patent 7937647 Error-detecting and correcting FPGA architecture
US Patent 07937647 Error-detecting and correcting FPGA architecture
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