Patent attributes
A semiconductor integrated circuit capable of maintaining characteristics of transistors in a circuit including a plurality of cascade connected transistors. The circuit includes an inverter which has a series connection of P-MOS transistors and a pair of N-MOS transistors. The P-MOS transistor is connected to a high potential source VH and the N-MOS transistor is connected to a low potential source VL. The gate of each MOS transistor is connected to an input signal line. The inverter circuit further includes a P-MOS transistor connected between a node and input signal line, and an N-MOS transistor connected between a node of the N-MOS transistors and the input signal line. The gates of the P-MOS transistor and the N-MOS transistor are connected to an output signal line of the inverter circuit.
