Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Michael R. May0
Raymond L. Vargas0
Date of Patent
May 10, 2011
0Patent Application Number
118623120
Date Filed
September 27, 2007
0Patent Primary Examiner
Patent abstract
A clock system includes a phase locked loop, a phase divider, and a control module. The phase locked loop (PLL) produces a plurality of phase-offset output oscillations. The phase divider generates a clock signal from one or more of the plurality of phase-offset output oscillations based on a phase divider control signal. The control module generates the phase divider control signal based on a desired setting for the clock signal.
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