Patent attributes
A system and method for sharing a single synchronous dynamic random access memory (SDRAM) unit between two chips, each having an SDRAM controller. Each SDRAM controller is effectively divided into a control block and a data block. The first SDRAM controller drives or reads directly from the SDRAM unit's data bus instead of employing a dedicated data bus for communication between the first and second SDRAM units. The data section of the second SDRAM controller responds to requests from the first SDRAM controller as if the requests had come from the second SDRAM controller's own control block. In other embodiments of the present invention, the second SDRAM controller can accept control signals generated by the first SDRAM. If the second SDRAM controller detects that the first SDRAM controller is initiating a request, the second SDRAM controller terminates any active requests of its own using burst termination. Thereafter, the second SDRAM controller processes the first SDRAM controller's request with the SDRAM unit as appropriate.
