US Patent 7941719 IC testing methods and apparatus

A shift register circuit is provided for storing instruction data for the testing of an integrated circuit core. The shift register circuit comprises a plurality of stages, each stage comprising a serial input (si) and a serial output (so) and a parallel output (wir_output) comprising one terminal of a parallel output of the shift register circuit. A first shift register storage element (32) is for storing a signal received from the serial input (si) and providing it to the serial output (so) in a scan chain mode of operation. A second parallel register storage element (38) is for storing a signal from the first shift register storage element (32) and providing it to the parallel output (wir_output) in an update mode of operation. The stage further comprises a feedback path (40) for providing an inverted version of the parallel output (wir_output) to the first shift register storage element (32) in a test mode of operation.