US Patent 7941768 Photolithographic process simulation in integrated circuit design and manufacturing

A method, system, and related computer program products for computer simulation of a photolithographic process is described. In one embodiment, a method for designing an integrated circuit is provided. The geometrical design intent and process condition values are received for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit. The photolithographic process is simulated at the process condition values using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results.