Patent attributes
A testing circuit has scan chain segments (62,64,60) defined between parallel inputs (wpi[0] . . . wpi[N−1]) and respective parallel outputs (wpo[0] . . . wpo[N−1]). The scan chain segments comprise a bank (62) of cells of a shift register circuit, a core scan chain portion (62), a first bypass path around the core scan chain portion (62) and a second bypass path around the bank (60) of cells of the shift register circuit. This architecture enables loading of data in parallel into the core scan chain, or into the shift register (WBR). In addition, each scan chain segment also has a series latching element (80), and this provides additional testing capability. In particular, the shifting of data between the latching elements (80) can be used to test the bypass paths while the internal or external mode testing is being carried out. This testing can thus be part of a single ATPG procedure.
