US Patent 7947540 Multi-level semiconductor device and method of fabricating the same

A multi-level semiconductor device includes a first transistor on a semiconductor substrate, the first transistor including a first source/drain region, a semiconductor layer on the semiconductor substrate, a second transistor on the semiconductor layer, the second transistor including a second source/drain region in a first portion of the semiconductor layer, and a contact pattern extending from the first source/drain region and contacting a second portion of the semiconductor layer, wherein the second portion of the semiconductor layer has an impurity concentration that is greater than that of the second source/drain region.