Patent attributes
A sample rate converter circuit receives a first signal at a first sampling frequency and for outputs a second signal, representative of the first signal, having a second sampling frequency. The sample rate converter comprises: a buffer, for storing data samples received from said first signal; a first loop circuit, for receiving a first clock signal corresponding to the first sampling frequency and a second clock signal corresponding to the second sampling frequency, and for generating an estimate of a ratio of the first sampling frequency to the second sampling frequency; and a second loop circuit, for receiving the first clock signal, the second clock signal and the estimate of the ratio of the first sampling frequency to the second sampling frequency, and for outputting a write pointer so that the data samples can be stored in the buffer, and for outputting a read pointer so that the data samples can be read from the buffer, with a first offset between the read pointer and the write pointer, such that the first offset is substantially independent of the ratio of the first sampling frequency to the second sampling frequency.
