US Patent 7949833 Transparent level 2 cache controller
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Patent abstract
A digital system that connects to a bus that employs physical addresses comprises a processing core. A level one (L1) cache communicates with the processing core. A level two (L2) cache communicates with the L1 cache. Both the L1 cache and the L2 cache are indexed by virtual addresses and tagged with virtual addresses. A bus unit communicates with the L2 cache and with the bus.
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Patent Inventor Names
Geoffrey K. Yung0
Hong-Yi Chen0
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US Patent 07949833 Transparent level 2 cache controller US Patent 7949833 Transparent level 2 cache controller
Infobox
Patent Number
079498330
Patent Number
79498330
Edits on 26 Sep, 2022
Golden AI
Infobox
Is a
Patent Jurisdiction
Patent Number
079498330
Date of Patent
May 24, 2011
0Patent Application Number
127285830
Date Filed
March 22, 2010
0Patent Primary Examiner
Edits on 7 Dec, 2021
Golden AI
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Infobox (+7 properties)
US Patent 07949833 Transparent level 2 cache controller
Infobox
Is a
Patent jurisdiction
Patent number
07949833
Date of patent
May 24, 2011
Patent application number
12728583
Date Filed
March 22, 2010
Patent primary examiner
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