Patent attributes
A programmable logic device is presented. The device comprises a plurality of logic elements and a plurality of I/O pins; a multiplexer and/or a de-multiplexer unit. The multiplexer and/or multiplexer unit is coupled between said logic elements and I/O pins. The device further comprises a control unit for generating control signal/s for selecting one of the inputs of the multiplexer and/or one of the outputs of the de-multiplexer. The control unit includes inputs for receiving a first clock signal, a second clock signal and indicators, said indicators being indicative of a phase skew relation amongst the clock signals. The control unit being configured for generating adaptively adjusted control signal/s according to the clock signals and indicators, said control signal/s are adaptively adjusted for eliminating impact of the phase skew amongst the clock signals.
