US Patent 7952907 Ferroelectric random access memory device

An FRAM device includes first ferroelectric capacitors, second ferroelectric capacitors, first plate lines and second plate lines. The first ferroelectric capacitors can be connected between word lines and bit lines. The second ferroelectric capacitors can be connected between the word lines and bit line bars. The first plate lines can be connected to upper electrodes of the first ferroelectric capacitors. The second plate lines can be connected to upper electrodes of the second ferroelectric capacitors. Thus, the first ferroelectric capacitors connected to the bit lines and the second ferroelectric capacitors connected to the bit line bars can be connected to the different plate lines, so that data can be output from any one of the bit line and the bit line bar. As a result, a layout of a core region can be simplified.