Patent attributes
A semiconductor device manufacturing method in which a semiconductor chip is connected to first and second lead frames. Source and gate electrodes extending over a first main surface of the semiconductor chip are connected to first electrode plates of the first lead frame and a drain electrode on the second main surface of the semiconductor chip, opposite to the first main surface, is connected to a drain electrode plate of the second lead frame. A sealing body is formed to cover the semiconductor chip and lead frames, while leaving the top surface of the drain electrode plate exposed with respect to the sealing body. Unnecessary portions of the first and second lead frames are cut off and surface mounting terminals are formed from the portions of the first and second electrode plates projecting from the sealing body.
