Is a
Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Mou-Shiung Lin0
Jin-Yuan Lee0
Date of Patent
June 14, 2011
Patent Application Number
11842957
Date Filed
August 22, 2007
Patent Primary Examiner
Patent abstract
A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.
