Patent attributes
Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features (e.g., strained fins, a space between two fins that is approximately 0.5 to 3 times greater than a width of a single fin, a first dielectric layer on the inner sidewalls of each pair of fins with a different thickness and/or a different dielectric material than a second dielectric layer on the outer sidewalls of each pair of fins, etc.).
