Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Kenichi Osada0
Koichiro Ishibashi0
Masanao Yamaoka0
Shigezumi Matsui0
Date of Patent
June 14, 2011
Patent Application Number
12629981
Date Filed
December 3, 2009
Patent Citations Received
Patent Primary Examiner
Patent abstract
A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.
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