US Patent 7965549 Semiconductor integrated circuit device and method of operating same

A semiconductor integrated circuit device includes a memory cell array. In the memory cell array, first memory cells of floating gate type are mixed with second memory cells of floating gate type. The second memory cell is sandwiched between the first memory cells. The first memory cells of floating gate type are configured to store m-level data, where m is a natural number of 2 or more. The second memory cells of floating gate type is configured to store n-level data, where n is a natural number greater than m.