US Patent 7966597 Method and system for routing of integrated circuit design

The invention relates to a method and a system for routing electric circuits in integrated circuit chip design. Specifically, the invention encompasses the steps of performing a congestion analysis for a given routed placement of cells containing said electric circuits on a chip; defining a critical area on said chip based on congestion information; analyzing actual wiring quality within said critical area; comparing an actual wiring quality of said critical area with a reference wiring quality of said critical area; and rerouting said critical area based on a comparison between the actual wiring quality and the reference wiring quality.