Patent attributes
A semiconductor device is provided which includes a semiconductor substrate (10), an ONO film (16) provided on the semiconductor substrate (10), and a bit line (14) formed in the semiconductor substrate (10) and connected to a contact (34) provided on the bit line (14), the semiconductor substrate (10) having trench isolation regions (50) provided at both sides of the bit line (14), the contact (34) being interposed between the trench isolation regions (50). Accordingly, even if the bit line (14) and the contact (34) is overlapped in a misaligned manner in a direction vertical to the bit line (14), the leakage current does not flow between the bit line (14) and the semiconductor substrate (10) via the contact (34), because the contact (34) is formed on the trench isolation region (50). This makes it possible to make the overlapping margin of the bit line (14) and the contact (34) large, thereby providing a semiconductor device in which the memory cell can be downsized.
