US Patent 7971174 Congestion aware pin optimizer
Patent 7971174 was granted and assigned to Cadence Design Systems on June, 2011 by the United States Patent and Trademark Office.
All edits
Edits on 15 May, 2024
Golden AI
Edits made to:
Infobox (+1 properties)
Infobox
Patent Citations Received
Edits on 28 Nov, 2023
Golden AI
Edits made to:
Article (+480 characters)
Article
Patent abstract
A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.
Edits on 19 Sep, 2023
Golden AI
Edits made to:
Infobox (+5 properties)
Infobox
Patent Inventor Names
Hitesh Marwah0
Mahendra Singh Khalsa0
Pawan Fangaria0
Sanjib Ghosh0
Vandana Gupta0
Edits on 25 May, 2023
Golden AI
Edits made to:
Infobox (+1/-1 properties)
US Patent 07971174 Congestion aware pin optimizer US Patent 7971174 Congestion aware pin optimizer
Infobox
Patent Number
079711740
Patent Number
79711740
Edits on 30 Mar, 2023
Golden AI
Infobox
Is a
Current Assignee
Patent Jurisdiction
Patent Number
079711740
Date of Patent
June 28, 2011
0Patent Application Number
122334140
Date Filed
September 18, 2008
0Patent Primary Examiner
Edits on 8 Dec, 2021
Golden AI
Edits made to:
Infobox (+8 properties)
US Patent 07971174 Congestion aware pin optimizer
Infobox
Is a
Current assignee
Patent jurisdiction
Patent number
07971174
Date of patent
June 28, 2011
Patent application number
12233414
Date Filed
September 18, 2008
Patent primary examiner
Find more entities like US Patent 7971174 Congestion aware pin optimizer
Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
