US Patent 7979766 Architecture for a message bus

An aspect of the present invention reduces the additional number of signal lines of a bus for control signals by using a set of signal lines to transfer data bits in some durations and to transfer control signals in some other durations. In one embodiment, the same signal lines are used to transfer data in a data transfer phase, and for bus arbitration in a bus arbitration phase. As a result, the total number of signal lines of a bus (bus width) is reduced. According to another aspect of the present invention, an arbitrator block allocates the bus to one of the requesting modules according to an assigned priority and least recently used (LRU) policy.