US Patent 7982498 System and method for power domain isolation

In one embodiment, a power domain isolation interface is disclosed. The interface has a level shifter having a signal input coupled to a first power domain and a memory element. The memory element has a signal input coupled to an output of the level shifter, an output coupled to a second power domain, and a hold enable input, wherein the memory element is configured to hold an input state when the hold enable input becomes asserted.