US Patent 7984232 Memory system

A memory system includes a NAND flash memory including a memory block containing a plurality of pages, and a controller which controls write of data to the flash memory, and includes a scrambling circuit which converts the data into a pseudo random number, wherein the scrambling circuit includes an initial value generator which generates an initial value for every segment, an initial value shifter which shifts the initial value by N bits for every page address, a pseudo random number generator which generates a pseudo random number sequence by an M-sequence by using the initial value shifted N bits, and a random number adder which adds the pseudo random number sequence to the data.