US Patent 7984406 Timing verification method and apparatus

A computer-implemented timing verification method for obtaining delay time for a signal propagated through a signal path and performing timing verification. The method stores a table including a wiring resistance variation amount and a wiring capacitance variation amount that are in accordance with a geometry deviation of a wire from a reference geometry, extracts a wiring structure of the signal path from a storage unit, extracts a wiring resistance variation amount and a wiring capacitance variation amount that correspond to the extracted wiring structure from the table, generates an on-chip-variation coefficient from the extracted wiring resistance variation amount and wiring capacitance variation amount, and calculates delay time for the signal propagated through the signal path based on the generated on-chip-variation coefficient.