US Patent 7993989 Vertical spacer forming and related transistor

Methods include, for example, forming a vertically disposed active region on a substrate; forming a first gate over a portion of the vertically disposed active region; forming a dielectric over the portion; exposing an upper surface of the first gate; forming a second gate over the upper surface; and forming a spacer pocket region between the vertically disposed active region, the first gate and the dielectric, wherein the spacer pocket region is self-aligned to a lower surface of the second gate and has a substantially uniform thickness from an upper to a lower extent thereof.